74ACT11112 dual j-k negative-edge-triggered flip-flop with clear and preset scas064a d3339, june 1989 revised april 1993 post office box 655303 ? dallas, texas 75265 copyright ? 1993, texas instruments incorporated 21 ? inputs are ttl-voltage compatible ? fully buffered to offer maximum isolation from external disturbance ? flow-through architecture optimizes pcb layout ? center-pin v cc and gnd configurations minimize high-speed switching noise ? epic (enhanced-performance implanted cmos) 1- m process ? 500-ma typical latch-up immunity at 125 c ? package options include plastic small-outline packages and standard plastic 300-mil dips description this device contains two independent j-k negative-edge-triggered flip-flops. a low level at the pre or clr input sets or resets the outputs regardless of the levels of the other inputs. when pre and clr are inactive (high), data at the j and k inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. following the hold-time interval, data at the j and k inputs may be changed without affecting the levels at the outputs. these versatile flip-flops can perform as toggle flip-flops by tying j and k high. the 74ACT11112 is characterized for operation from 40 c to 85 c. function table inputs outputs pre clr clk j k q q l h x x x h l h lxxxl h l lxxxh h h h llq 0 q 0 h h hlh l h h lhl h h h h h toggle h h h x x q 0 q 0 2 this configuration is nonstable; that is, it will not persist when either pre or clr returns to the inactive (high) level. d or n package (top view) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1pre 1q 1q gnd 2q 2q 2pre 2j 1j 1k 1clk 1clr v cc 2clr 2clk 2k epic is a trademark of texas instruments incorporated. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
74ACT11112 dual j-k negative-edge-triggered flip-flop with clear and preset scas064a d3339, june 1989 revised april 1993 post office box 655303 ? dallas, texas 75265 22 logic symbol 2 5 2 clr 2j 2 pre 1 clk 1 pre 2q 10 8 7 13 15 16 1 9 1k 2clk 1 clr 6 2q 3 1q 2 1q s c1 1k r 1j 1j 14 11 2k s c2 2k r 2j 2 this symbol is in accordnace with ansi/ieee std 91-1984 and iec publication 617-42. logic diagram, each flip-flop (positive logic) tg tg tg c c c c q c c pre j k clk clr c c c c q tg absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 3 supply voltage range, v cc 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 1) 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o (see note 1) 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o (v o = 0 to v cc ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v cc or gnd 100 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. note 1: the input and output voltage ratings may be exceeded if the input and output current ratings are observed.
74ACT11112 dual j-k negative-edge-triggered flip-flop with clear and preset scas064a d3339, june 1989 revised april 1993 post office box 655303 ? dallas, texas 75265 23 recommended operating conditions min max unit v cc supply voltage 4.5 5.5 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v v i input voltage 0 v cc v v o output voltage 0 v cc v i oh high-level output current 24 ma i ol low-level output current 24 ma t/ v input transition rise or fall rate 0 10 ns/ v t a operating free-air temperature 40 85 c electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc t a = 25 c min max unit parameter test conditions v cc min typ max min max unit i oh =50 a 4.5 v 4.4 4.4 i oh = 50 a 5.5 v 5.4 5.4 v oh i oh =24ma 4.5 v 3.94 3.8 v i oh = 24 ma 5.5 v 4.94 4.8 i oh = 75 ma 2 5.5 v 3.85 i ol =50 a 4.5 v 0.1 0.1 i ol = 50 a 5.5 v 0.1 0.1 v ol i ol =24ma 4.5 v 0.36 0.44 v i ol = 24 ma 5.5 v 0.36 0.44 i ol = 75 ma 2 5.5 v 1.65 i i v i = v cc or gnd 5.5 v 0.1 1 a i cc v i = v cc or gnd, i o = 0 5.5 v 4 40 a i cc 3 v i = v cc or gnd 5.5 v 0.9 1 ma c i v i = v cc or gnd 5 v 3.5 pf 2 not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. 3 this parameter is the increase in supply current for each input that is at one of the specified ttl voltage levels rather than 0 v or v cc . timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 1) t a = 25 c min max unit min max min max unit f clock clock frequency 125 125 mhz t pulse duration pre or clr low 4 4 ns t w p u lse d u ration clk high or low 4 4 ns t setu p time before clk ???? ???? ?? ??? ?? ? ?? ? ? ??? ??? ????? ??k ?? ?? ?? ???????? ? ? ?? ? ? ???? ??? ????? ??k 1.5 1.5 ns
74ACT11112 dual j-k negative-edge-triggered flip-flop with clear and preset scas064a d3339, june 1989 revised april 1993 post office box 655303 ? dallas, texas 75265 24 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 1) parameter from to t a = 25 c min max unit parameter (input) (output) min typ max min max unit f max 125 125 mhz t plh pre or clr qorq 1.5 3.6 6.3 1.5 6.8 ns t phl pre or clr q or q 1.5 4.6 7.4 1.5 8 ns t plh clk qorq 1.5 4.2 7 1.5 7.7 ns t phl clk q or q 1.5 4.7 7.4 1.5 8.4 ns operating characteristics, v cc = 5 v, t a = 25 c parameter test conditions typ unit c pd power dissipation capacitance per flip-flop c l = 50 pf, f = 1 mhz 39 pf parameter measurement information 50% v cc 1.5 v 1.5 v 1.5 v 3 v 3 v 0 v 0 v t h t su voltage waveforms data input t plh t phl t phl t plh v oh v oh v ol v ol 1.5 v 1.5 v 3 v 0 v 50% v cc 50% v cc input (see note b) out-of-phase output in-phase output timing input (see note b) 50% v cc voltage waveforms 3 v 0 v 1.5 v 1.5 v t w voltage waveforms input load circuit from output under test c l = 50 pf (see note a) 500 w notes: a. c l includes probe and jig capacitance. b. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r = 3 ns, t f = 3 ns. c. the outputs are measured one at a time with one input transition per measurement. figure 1. load circuit and voltage waveforms
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